Method of arranging a plurality of semiconductor structural elements on a carrier and carrier comprising a plurality of semiconductor structural elements
US10381311B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Aug 3, 2016 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of arranging a plurality of semiconductor structural elements on a carrier includes arranging at least some of the semiconductor structural elements in multiple groups G and at least one semiconductor structural element of a group G has a property E that determines the position of the respective group G of semiconductor structural elements on the carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.