Interface engineering for high capacitance capacitor for liquid crystal display
US10381454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.