System and fabrication method of piezoelectric stack that reduces driving voltage and clamping effect
US10381544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2015 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T117/1092
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A system and method provides a piezoelectric stack arrangement for reduced driving voltage while maintaining a driving level for active piezoelectric materials. A stack arrangement of d36 shear mode <011>single crystals of both air X-cut and Y-cut ±1:45° (±20°) arrangement are bonded with discrete conductive pillars to form a shear crystal stack. The bonding area between the neighboring crystal parts is minimized. The bonding pillars are positioned at less than a total surface are of the single crystal forming the stack. The stack fabrication is facilitated with a precision assembly system, where crystal parts are placed to desired locations on an assembly fixture for alignment following the preset operation steps. With the reduced clamping effect from bonding due to lower surface coverage of the discrete conductive pillars, such a piezoelectric d36 shear crystal stack exhibits a reduced driving voltage while maintaining a driving level and substantial and surprisingly improved performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.