Optimum phase searching system and method thereof in ethernet physical layer
US10382047B1 · kind B1 · utility
5Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jun 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for optimum phase searching in an Ethernet physical layer includes a time recovering circuit and an equalizer. The time recovering circuit includes a loop filter and a time error detector, and the equalizer includes a feed forward equalizer, a slicer and a feed backward equalizer. An optimum phase searching method includes obtaining optimum phases when mean squared errors calculated by the slicer are less than a first threshold, absolute values of mean values of outputs calculated by a time error detector are less than a second threshold, and the outputs are monotonic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.