Memory controller with adjustable impedance for output terminal
US10382232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.