Method for managing the operation of a test mode of a logic component with restoration of the pre-test state
US10386414B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 28, 2015 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.