Efficient use of buffer space in a network switch
US10387074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2016 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.