Systems and methods for modeling integrated clock gates activity for transient vectorless power analysis of an integrated circuit
US10387595B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jul 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are embodiments of systems and methods for a deterministic modeling of integrated clock gate (ICG) activity in a vectorless power analysis of a synthesized integrated circuit (IC) design. The systems and methods may generate a priority list of the ICGs based on the slack values of the outputs of the ICGs calculated from a static timing analysis (STA). The system and method may further receive one or more priority inputs from the user and select the ICGs to be activated during power analysis based on the priority list and the priority inputs from the user. The systems and methods may propagate a set of state stimuli through the output cones of the selected ICGs and calculate the current through and power consumed by circuit devices in the output cones based on the state propagation and global data activity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.