Spiking neural network with reduced memory access and reduced in-network bandwidth consumption
US10387770B2 · kind B2 · utility
1Cited by
7References
20Claims
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Key dates
| Filing date | Mar 7, 2016 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/049
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A spiking neural network having a plurality layers partitioned into a plurality of frustums using a first partitioning may be implemented, where each frustum includes one tile of each partitioned layer of the spiking neural network. A first tile of a first layer of the spiking neural network may be read. Using a processor, a first tile of a second layer of the spiking neural network may be generated using the first tile of the first layer while storing intermediate data within an internal memory of the processor. The first tile of the first layer and the first tile of the second layer belong to a same frustum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.