Memory cell and array having device, P-type transistor and N-type transistor
US10388346B2 · kind B2 · utility
1Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.