Write assist circuit for lowering a memory supply voltage and coupling a memory bit line
US10388365B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.