Protected electronic chip
US10388724B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Oct 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.