FET with buried gate structure

US10388746B2 · kind B2 · utility

Assignee

• TELEDYNE SCIENTIFIC & IMAGING, LLC · US

Inventors

• Keisuke Shinohara · Thousand Oaks, US
• Miguel Urteaga · Moorpark, US
• Casey King · Austin, US
• Andy Carter · Thousand Oaks, US

Key dates

• Filing date: Jul 6, 2017
• Grant date: Aug 20, 2019
• Expiry date: Jul 6, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.