Semiconductor structure having a high voltage well region
US10388758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jan 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.