Apparatus and methods for power efficient CMOS and BiCMOS transmitters suitable for wireless applications
US10389316B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2019 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Feb 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0408
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A silicon based (e.g., SiGe, CMOS, or BiCMOS) transmitter includes an algorithm that strategically segment and pre-distort the input signal according to its power; a reconfigurable power amplifier (PA) having a plurality of PA sections, wherein the plurality of PA sections comprise discrete weighted transistor arrays that are digitally turned OFF or ON according to a magnitude of an input signal; an impedance matching network equipped with a common-mode feedback (CMFB) mechanism configured to reduce common-mode glitches at an output of the PA due to ON/OFF manipulations of the PA segments; and a 1:N transformer, which comprises a capacitive matching engine and a power detector, disposed between the impedance matching network and the reconfigurable linear PA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.