Patent · US Active

Synchronize-able modular physical layer architecture for scalable interface

US10389341B1 · kind B1 · utility

1Cited by

9References

10Claims

0Family size

Assignee

Altera Corporation · US

Inventor

Chee Hak Teh · Kampung Bukit Kechil, MY

Key dates

Filing date	Dec 28, 2015
Grant date	Aug 20, 2019
Priority date	—
Expiry date	Mar 17, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00234
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and an input-output module that provides outbound control and data streams and receives inbound control and data streams.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.