Ultra low power linear voltage regulator
US10394263B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for voltage regulation includes reducing a power consumption of a voltage regulator during an IDLE phase, by disabling a feedback loop configured to regulate an internal voltage to a multiple of a reference voltage in response to the voltage regulator receiving a digital signal from a digital circuit. The internal voltage is proportional to an external voltage supplied to the digital circuit. A regulated accuracy of the external voltage is increased during a MEASUREMENT phase by enabling the feedback loop in response to the voltage regulator receiving the digital signal from the digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.