Back bias regulator circuit and method therefor
US10394264B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.