Implementing hierarchical PCI express switch topology over coherent mesh interconnect
US10394747B1 · kind B1 · utility
16Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 31, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.