Patent · US Active

Integrated circuit for operating on a bus, and method for operating the integrated circuit

US10394748B2 · kind B2 · utility

0Cited by

5References

10Claims

0Family size

Assignee

CPT Group GmbH · US

Inventors

Bernhard Bieg · Regensburg, DE
Christoph Haggenmiller · Munich, DE
Klaus Schneider · Lappersdorf, DE
Andrey Shadrin · Saint Petersburg, RU

Key dates

Filing date	Jan 25, 2018
Grant date	Aug 27, 2019
Priority date	—
Expiry date	Jan 25, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a reception port an address port, and a memory with a number of memory sections for storing activation information. The number of memory sections is equal to the number, encodable by the address port, of activatable integrated circuits that are operable over a common bus. A control unit is configured to compare the address encoded by the address port with an address received at the reception port. The control unit writes a defined bit pattern to the memory section associated with the address in the event of a positive comparison, and withholds transmission of a negative acknowledgement signal in the event of a negative comparison. The integrated circuit is configured to be activated by the defined bit pattern in the memory section that corresponds to the address defined at the address port, for communicating with a microprocessor connected to the integrated circuit via the common bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.