Method to automatically generate and promote timing constraints in a Synopsys Design Constraint format
US10394983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of promoting timing constraints in an electronic design automation process of a chip is provided. A method of promoting a lower level block's timing constraint to an upper level block by providing an option to preserve the timing intent of the lower level block at the same time, or to modify the timing constraint such that the block level timing is in context to the top level block timing is provided. The method implements automatic promotion of timing constraint in different modes as an integration mode; an isolation mode and combination thereof, wherein the integration mode is independent of SDCs; and the isolation mode is based on the input SDCs. A method of automatically promoting constant values that are defined through a set_case_analysis command in the SDC file is further provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.