Majority logic synthesis
US10394988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator ′. The method further comprises providing a commutativity, a majority (Ω.M), an associativity (Ω.A), a distributivity (Ω.D), an inverter propagation (Ω.I), a relevance (Ψ.R), a complementary associativity (Ψ.C), and a substitution (Ψ.S) transformation; and combining the Ω.M, Ω.C, Ω.A, Ω.D, Ω.I, Ψ.R, Ψ.C and Ψ.S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the Ω.A, Ω.C, Ω.D, Ω.I, Ψ.R, Ψ.S and Ψ.C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the Ω.M transformation, applied left-to-right, and the Ω.D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.