Three-dimensional semiconductor devices
US10396094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.