Thin film transistor including a vertical channel and display apparatus using the same
US10396140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/123
Abstract
A thin film transistor includes a substrate and a gate electrode disposed over the substrate. The gate electrode includes a center part and a peripheral part configured to at least partially surround the center part. The thin film transistor further includes a gate insulating layer disposed below the gate electrode and a first electrode insulated from the gate electrode by the gate insulating layer. The first electrode has at least a portion thereof overlapping the center part. The thin film transistor additionally includes a spacer disposed below the first electrode and a second electrode insulated from the first electrode by the spacer. The second electrode has at least a portion thereof overlapping the peripheral part. The thin film transistor further includes a semiconductor layer connected to the first and second electrodes, and insulated from the gate electrode by the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.