Thin film transistor array panel
US10396212B2 · kind B2 · utility
3Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Jan 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor array panel according to an exemplary embodiment includes: a substrate; a metal pattern positioned on the substrate; a buffer layer positioned on the metal pattern; and a semiconductor layer positioned on the buffer layer and including a source region, a channel region, and a drain region, wherein the metal pattern overlaps at least one of the source region and the drain region, and the metal pattern does not overlap the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.