Parasitic capacitance cancellation using dummy transistors

US10396766B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Basavaraj G. Gorguddi · Bengaluru, IN
• Ani Xavier · Kanchinakote, IN

Key dates

• Filing date: Dec 26, 2017
• Grant date: Aug 27, 2019
• Expiry date: Dec 26, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/124
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some examples, an apparatus includes a plurality of first transistors coupled to a first input terminal and a first output terminal. The apparatus also includes a plurality of second transistors coupled to a second input terminal and a second output terminal. The apparatus further includes a plurality of first dummy transistors coupled to the first input terminal and the second output terminal. The apparatus also includes a plurality of second dummy transistors coupled to the second input terminal and the first output terminal.