Patent · US Active

Fractional-N phase lock loop apparatus and method using multi-element fractional dividers

US10396808B2 · kind B2 · utility

6Cited by

2References

20Claims

0Family size

Assignee

The Board of Regents of the University of Texas System · US

Inventor

Nan Sun · Beijing, CN

Key dates

Filing date	Mar 15, 2017
Grant date	Aug 27, 2019
Priority date	—
Expiry date	Mar 15, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.