Patent · US Active

Self-testing of a phase-locked loop using a pseudo-random noise

US10396974B1 · kind B1 · utility

3Cited by

6References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Jan-Peter Schat · Hamburg, DE
Ulrich Moehlmann · Hamburg, DE

Key dates

Filing date	Jul 20, 2018
Grant date	Aug 27, 2019
Priority date	—
Expiry date	Jul 20, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/0212
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.