Multi-chip structure having flexible input/output chips
US10397142B2 · kind B2 · utility
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8References
21Claims
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Key dates
| Filing date | Feb 23, 2016 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Mar 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.