Voltage suppressor test circuit and method of testing a voltage suppressor
US10401420B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Jan 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2632
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system for testing a transient voltage suppressor (TVS) configured to be coupled between a bus and a first ground or line to discharge a voltage surge on the bus to the first ground or line includes a pulse source configured to generate an electrical pulse. The system further includes a transformer having a first side coupled to the pulse source and a second side configured to be coupled to the TVS and configured to transfer the electrical pulse to the TVS and to transfer an at least partial reflection of the electrical pulse from the TVS to the first side. The system also includes a test point coupled to the first side of the transformer and configured to receive the at least partial reflection of the electrical pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.