Method and apparatus for detecting memory conflicts using distinguished memory addresses
US10402201B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Mar 9, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Apr 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for detecting potential memory conflicts in a parallel computing environment by executing two parallel program threads. The parallel program threads include special operands that are used by a processing core to identify memory addresses that have the potential for conflict. These memory addresses are combined into a composite access record for each thread. The composite access records are compared to each other in order to detect a potential memory conflict.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.