Reducing traffic in hierarchical cache interconnects
US10402329B1 · kind B1 · utility
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19Claims
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Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A congestion controller may be configured to control traffic on an interconnect between a higher level cache and a lower level cache. The lower level cache may also be coupled to a main memory. The congestion controller may be configured to reduce congestion on the interconnect by blocking transactions that include writing of data to the lower level cache if the data has not been modified relative to a copy of the data in the main memory. The congestion controller may also be configured to control the traffic by blocking certain transactions in a controlled manner for traffic shaping or for performance features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.