System, apparatus and method for overriding of non-locality-based instruction handling
US10402336B2 · kind B2 · utility
3Cited by
0References
20Claims
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Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | May 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes: a core including a decode unit to decode a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; and a locality controller to determine whether to override the no-locality hint based at least in part on one or more performance monitoring values. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.