System and method for processing interrupts by processors of a microcontroller in a low-power mode
US10402353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.