Patent · US Active

Hardened white box implementation

US10403174B2 · kind B2 · utility

0Cited by

0References

16Claims

0Family size

Assignee

GIESECKE+DEVRIENT MOBILE SECURITY GMBH · DE

Inventors

Hermann Drexler · Munich, DE
Sven Bauer · Vaterstetten, DE
Jürgen Pulkus · Hersbruck, DE

Key dates

Filing date	Oct 30, 2015
Grant date	Sep 3, 2019
Priority date	—
Expiry date	Aug 23, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/16
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A processor device has an executable implementation of a cryptographic algorithm implemented thereon that is white-box-masked by a function f. The implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T′ by means of an invertible function f. As a mapping f there is provided a combination (f=(c1, c2, . . . )*A) of an affine mapping A having an entry width BA and a number of one or several invertible mappings c1, c2, . . . having an entry width Bc1, Bc2, . . . respectively, wherein BA=Bc1+Bc2+ . . . . Output values w are generated altogether by the mapping f. The affine mapping A is constructed by a construction method coordinated with the invertible mappings c1, c2, and etc.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.