Display panel
US10403221B2 · kind B2 · utility
8Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.