Patent · US Active

Hybrid flash memory structure

US10403342B2 · kind B2 · utility

1Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 19, 2018
Grant dateSep 3, 2019
Priority date
Expiry dateJun 19, 2038

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A memory system includes a code flash and data flash merged flash memory, which may contain a code flash with differential cell structure, a data flash with single cell structure, decoder circuitry, a sense amplifier, and other suitable support circuitry. The code flash and data flash may be located in a same plane or multi planes. In some examples, the code flash may be also accessed to read while the data flash is performing write operation, and vice versa.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.