Display device and method of manufacturing the same
US10403649B2 · kind B2 · utility
0Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/124
Abstract
A display device includes a common active pattern, a first gate electrode, and a second gate electrode. The common active pattern includes an NMOS area, a PMOS area, and a silicide area in a same layer as the NMOS area and the PMOS area. The silicide area electrically connects the NMOS area to the PMOS area. The NMOS area includes a first channel area and an n-doped area contacting the first channel area. The PMOS area includes a second channel area and a p-doped area contacting the second channel area. The first gate electrode overlaps the first channel area, and the second gate electrode overlaps the second channel area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.