Mask for manufacturing TFT in 4M production process and TFT array manufacturing method of 4M production process
US10403654B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0273
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a mask for manufacturing a TFT in a 4M production process and a TFT array manufacturing method of a 4M production process. For the mask for manufacturing a TFT in a 4M production process, in a TFT layout structure of the mask, a line pattern is provided adjacent to an outer edge of a TFT pattern to extend along the outer edge of the TFT pattern. The present invention also provides a corresponding TFT array manufacturing method of the 4M production process, which uses the mask of the present invention to serve as a mask for a second mask-based process. The mask for manufacturing a TFT in a 4M production process according to the present invention allows for achievement of an edge-thinned structure through variation of edge exposure of the mask so as to make plasma etching more easily performed on such a structure to thereby reduce residues of amorphous silicon and heavily-doped silicon on an edge of a second metal layer. The TFT array manufacturing method of the 4M production process of the present invention is such that the mask of the present invention is used in combination with a 4M production process to alleviate the problems of residues of amorpho…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.