Clock delay adjusting circuit based on edge addition and integrated chip thereof
US10404243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Apr 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof. The clock delay adjusting circuit comprises a clock delay unit, a weight coefficient unit and an edge addition unit, wherein the clock delay unit is used for conducting equal-interval delay on clock signals inputted into the input end of the clock delay unit to obtain and output at least three delay clock signals at equal intervals, the weight coefficient unit is used for generating weight signals with the number the same as the number of the delay clock signals according to digital codes inputted into the input end of the weight coefficient unit and outputting the weight signals, and the edge addition unit is used for receiving the delay clock signals and the weight signals, conducting weighted summation on the delay clock signals according to the weight signals and outputting signals obtained through weighted summation to obtain new clock signals with continuous clock rising edges/continuous clock falling edges, wherein the number of the new clock signals is the same as the number of the delay clock signals. In addition, the clock delay adjusting circuit can be made into …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.