Apparatus and methods for reducing clock-ungating induced voltage droop
US10409317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jun 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.