Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline
US10409601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions. For example, one embodiment of a processor comprises: a decoder to decode a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode, first and second source operands, and at least one destination operand, the broadcast instruction having a split value associated therewith; a first source register associated with the first source operand to store a first plurality of packed data elements; a second source register associated with the second source operand to store a second plurality of packed data elements; execution circuitry to execute the operations of the decoded broadcast instruction, the execution circuitry to copy a first number of contiguous data elements from the first source register to a first set of contiguous data element locations in a destination register specified by the destination operand, the execution circuitry to further copy a second number of contiguous data elements from the second source register to a second set of contiguous data eleme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.