Multi-core processor supporting cache consistency, method, apparatus and system for data reading and writing by use thereof
US10409723B2 · kind B2 · utility
3Cited by
30References
27Claims
0Family size
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Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Dec 14, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.