System, apparatus and method for selective enabling of locality-based instruction handling
US10409727B2 · kind B2 · utility
1Cited by
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19Claims
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Key dates
| Filing date | Mar 31, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.