Systems and methods for mapping matrix calculations to a matrix multiply accelerator
US10409889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.