Patent · US Active

Static memory cell capable of balancing bit line leakage currents

US10410687B2 · kind B2 · utility

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1References

2Claims

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Assignee

Ningbo University · CN

Inventors

Pengjun Wang · Zhejiang, CN
Keji Zhou · Zhejiang, CN
Yuejun Zhang · Zhejiang, CN
Huihong Zhang · Zhejiang, CN

Key dates

Filing date	Aug 22, 2018
Grant date	Sep 10, 2019
Priority date	—
Expiry date	Aug 22, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A static memory cell capable of balancing bit line leakage currents is characterized by including a 1st PMOS transistor, a 2nd PMOS transistor, a 1st NMOS transistor, a 2nd NMOS transistor, a 3rd NMOS transistor, a 4th NMOS transistor, a 5th NMOS transistor, a 6th NMOS transistor, a 7th NMOS transistor, an 8th NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1st NMOS transistor, the 2nd NMOS transistor, the 3rd NMOS transistor and the 4th NMOS transistor are all normal threshold NMOS transistors. The 1st PMOS transistor and the 2nd PMOS transistor are both low threshold PMOS transistors. The 5th NMOS transistor, the 6th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.