Semiconductor devices
US10410722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | May 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.