Non-volatile memories and data reading methods thereof
US10410727B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 5, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Jul 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.