Methods of forming wiring structures for semiconductor devices
US10410919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76873
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.