Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits
US10410975B1 · kind B1 · utility
1Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2015 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Sep 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.